If you are running into the following error (Adept, or other programmer), here is how to fix it in Xilinx.
I came across this issue when using my Basys 2 and trying to load a bit file with Digilent's Adept programmer. It is only a compatibility issue with the bit file and FPGA board.
Startup clock for this file is'CCLK' instead of 'JTAG CLK'. Problems will likely occur.
Associate config file with device anyway?
Generate Programming File
Process -> Process Properties -> Startup Options -> FPGA Start-Up Clockand change it to