Heya, Thanks for visiting!

CCLK to JTAG Clock: Bit File Programming Error Fix

  • xilinx
  • bit-file
  • fpga
  • clock

If you are running into the following error (Adept, or other programmer), here is how to fix it in Xilinx.

I came across this issue when using my Basys 2 and trying to load a bit file with Digilent's Adept programmer. It is only a compatibility issue with the bit file and FPGA board.

Startup clock for this file is'CCLK' instead of 'JTAG CLK'. Problems will likely occur.
Associate config file with device anyway?

  1. In the Processes pane, select Generate Programming File
    Xilinx Processes pane
  2. Then go to Process -> Process Properties -> Startup Options -> FPGA Start-Up Clock and change it to JTAG CLK.
    Xiline Process context menu highlighting "Process Properties..." Xiline process properties window with "JTAG Clock" selected
  3. Click, OK. Then re-generate the programming file and program your board.