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Just finished the classic tennis game Pong for my Basys 2 FPGA. The project is written in VHDL and is played on a VGA monitor. Built from scratch. You can see a video of it in action at the bottom of this article. Features: Multiplayer: Battle against your friend Play against the AI. Or AI vs AI battles Score Keeping Hidden Mode / Easter Egg Source: Just visit the Github Repo. Controls: Action Control Player Left/1 Paddle movement btn2 and btn3 Player Right/2 Paddle movement btn0 and btn1 Reset switch0 Player Left/1 AI Enable switch7 Player Right/2 AI Enable switch6 Technology: Here just a list of things implemented in this design Collision Detection and Resolution VGA Output, game video Text ...
If you are running into the following error (Adept, or other programmer), here is how to fix it in Xilinx. I came across this issue when using my Basys 2 and trying to load a bit file with Digilent's Adept programmer. It is only a compatibility issue with the bit file and FPGA board. Startup clock for this file is'CCLK' instead of 'JTAG CLK'. Problems will likely occur. Associate config file with device anyway? In the Processes pane, select Generate Programming File Then go to Process -> Process Properties -> Startup Options -> FPGA Start-Up Clock and change it to JTAG CLK. Click, OK. Then re-generate the programming file and program your board.
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