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Go straight to the VGA Simulator About The VGA Simulator is a web based tool to easily view a raw VGA signal without having to hook it up to an actual CRT monitor. Easily review and save any frames generated. It uses horizontal sync, vertical sync, and red, green, blue to recreate pixel perfect frames. The image below is a scaled down version of the real thing so mind the blurryness: The purpose of this tool was to create a faster way to debug FPGA/VHDL projects that utilize VGA. The problem is that synthesizing and generating a bit-file takes too long with Xilinx mainly because it only utilizes a single core. Although we have Simulators such as Isim to debug ...
If you are running into the following error (Adept, or other programmer), here is how to fix it in Xilinx. I came across this issue when using my Basys 2 and trying to load a bit file with Digilent's Adept programmer. It is only a compatibility issue with the bit file and FPGA board. Startup clock for this file is'CCLK' instead of 'JTAG CLK'. Problems will likely occur. Associate config file with device anyway? In the Processes pane, select Generate Programming File Then go to Process -> Process Properties -> Startup Options -> FPGA Start-Up Clock and change it to JTAG CLK. Click, OK. Then re-generate the programming file and program your board.